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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Index
Page 374 of 377
750gx_umIX.fm.(1.2)
March 27, 2006
DABR, 62
DAR
, 61
DEC
, 62
DSISR
, 61
EAR
, 62
HID0
, 65, 337
HID1
, 70
IABR
, 64
ICTC
, 77, 348
L2CR
, 81, 329
MMCR0
, 72, 172, 351
MMCR1
, 74, 172, 351
MSR
, 60
PMC1 and PMC2
, 44
PMCn
, 74, 172
PVR
, 60
SDR1
, 61
SIA
, 75, 172, 355
SPRGn
, 61
SPRs for performance monitor
, 349
SRn
, 61
SRR0/SRR1
, 61
THRMn
, 78
time base (TB)
, 62
user-level
CR
, 59
CTR
, 59
FPRn
, 59
FPSCR
, 59
GPRn
, 59
LR
, 59
time base (TB)
, 60, 62
UMMCR0
, 73
UMMCR1
, 74
UPMCn
, 75
USIA
, 76, 355
XER
, 59
Rename buffer, definition
, 210
Rename register operation
, 224
Reservation station, definition
, 210
Reserved instruction class
, 89
Reset
HRESET signal, 272
reset exception
, 163
SRESET
signal, 272
Retirement, definition
, 210
rfi
, 161
Rotate/shift instructions
, 95
RSRV
(reserve) signal, 319
S
SDR1 register, 61
Segment registers
SR description, 61
SR manipulation instructions
, 119
Segmented memory model, see Memory management
unit
Serializing instructions
, 225
Shift/rotate instructions
, 95
SIA (sampled instruction address) register
, 75, 172, 355
Signals
AACK
, 262
ABB
, 285
address arbitration
, 251, 285
address transfer
, 292
address transfer attribute
, 294
An
, 254
ARTRY
, 263, 303
BG
, 252, 285
BR
, 251, 285
CI
, 260
CKSTP_IN
/CKSTP_OUT, 169, 271
configuration
, 250
COP/scan interface
, 319
data arbitration
, 285, 301
data transfer termination
, 303
DBB
, 286, 302
DBG
, 264, 285
DBWO
, 286, 303, 320
DHn/DLn
, 266
DRTRY
, 269, 303, 306
GBL
, 261
HRESET
, 272
MCP
, 62, 152, 271
PLL_CFGn
, 277
power and ground signals
, 278
QACK
, 273
QREQ
, 273
RSRV
, 319
SRESET
, 272
TA
, 268
TBST
, 259, 294, 303
TEA
, 269, 303, 307
transfer encoding
, 256
TS
, 253
TSIZn
, 258, 294
TTn
, 256, 294
WT
, 260
Single-beat transfer
reads with data delays, timing, 312
reads, timing
, 310
termination
, 304
writes, timing
, 311
Snooping
, 142
SPRGn registers
, 61
SRESET
(soft reset) signal, 272
SRR0/SRR1 (status save/restore registers)
description, 61
exception processing
, 156
Stage, definition
, 211