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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_09.fm.(1.2)
March 27, 2006
L2 Cache
Page 331 of 377
9.6.1.1 Loading the Locked L2 Cache
Contents are loaded into the L2 cache simply by executing load instructions to cacheable addresses that
miss in the L1. Note that instructions to be locked in the L2 cache are loaded as data. Only one access to
each 32-byte cache block is needed to allocate the entire block in the cache.
Note: While lines are being allocated in way 0 using this procedure, the cache behaves as a direct-mapped
cache. Therefore, the various blocks of code and data must be located in physical memory such that each
line is in a unique equivalence class with respect to the organization of the L2 cache. Each way contains
256 KB, consisting of 4096 lines of two 32-byte sectors.
In addition to the constraint imposed by the cache associativity, it is important while loading the contents to be
locked that no spurious lines are allocated. The use of the ‘data only’ mode prevents the current instruction
stream from being allocated. To prevent unwanted data from being allocated, the load sequence must either
avoid using other data (for example, by using immediate fields in the instructions to specify load addresses)
or must prevent that data from colliding with other data or instructions to be allocated (for example, by allo-
cating it explicitly as part of the data to be locked).
The contents of the locked cache cannot be deallocated implicitly under normal conditions (see the excep-
tions for snoops and stwcx. marked write through described above), but can be deallocated by the processor
using a dcbi instruction, as described below.
9.6.1.2 Locked Cache Operation
When one or more ways of the L2 cache are locked, the locked ways behave like the normal (unlocked)
cache except in the following situations:
Replacement never occurs in the locked cache. If one way is locked, an L2 miss causes replacement in
one of the unlocked ways of the cache by the new block of data or instructions received from the bus (or
from the L1 cache in the case of a castout). If all ways are locked, an L2 miss causes the new block of
data or instructions from the bus to be forwarded to the L1 cache without updating the L2. In the case of a
castout that misses in a completely locked L2, the data is forwarded to the bus from the L1 without updat-
ing the L2. Although the locked cache is not kept coherent with main memory in general, a store access
marked write-through that hits in a locked way updates the L2 as usual and is also forwarded to the bus.
An stwcx. marked cache-inhibited that hits in a locked way invalidates the corresponding cache line, and also
gets forwarded to the 60x bus. The locked cache is snooped and responds identically to an unlocked cache,
which might also result in the invalidation of locked cache lines. The L2CR[SHEE] bit can be set to enable
such an event to raise a machine check. The L2CR[SHERR] bit is a sticky bit that records the occurrence of
an invalidation in a locked line. This bit can be cleared by a Move-to Special-Purpose Register (mtspr)
instruction to the L2CR. Note that Load Word and Reserve Indexed (lwarx) and stwcx. instructions should
not be used with locked cache addresses when trying to synchronize outside the processor, since the locked
memory is not shared externally. More generally, coherency is not maintained for locked addresses. Any
updates to locked memory that must be reflected outside the processor must be made through software, by
cache-inhibited operations or copies to other addresses.
A dcbst instruction is used to update external memory with the more recent contents of the internal cache. A
dcbf instruction also does this, while invalidating the internal copy. A dcbf or dcbst that hits in the locked
cache modifies the locked cache with the castout block if it hit in the L1 cache, but does nothing if it missed in
the L1 cache (the corresponding behavior for a hit in the normal L2 cache is to invalidate the block if the
access hit in the L1, and to flush the block if it missed in the L1).