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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_01.fm.(1.2)
March 27,2006
PowerPC 750GX Overview
Page 51 of 377
1.8 Memory Management
The following subsections describe the memory-management features of the PowerPC Architecture, and the
750GX implementation. A detailed description of the 750GX MMU implementation is provided in Chapter 5,
Memory Management, on page 179.
1.8.1 PowerPC Memory-Management Model
The primary functions of the MMU are to translate logical (effective) addresses to physical addresses for
memory accesses and to provide access protection on blocks and pages of memory. There are two types of
accesses generated by the 750GX that require address translation—instruction fetches, and data accesses
to memory generated by load, store, and cache-control instructions.
The PowerPC Architecture defines different resources for 32-bit and 64-bit processors. The 750GX imple-
ments the 32-bit memory-management model. The memory management unit provides two types of memory-
access models: block-address translate (BAT) model and a virtual address model. The BAT block sizes
range from 128 KB to 256 MB, are selectable from high-order effective address bits, and have priority over
the virtual model. The virtual model employs a 52-bit virtual address space made up of a 24-bit segment
address space and a 28-bit effective address space. The virtual model uses a demand paging method with a
4-KB page size. In both models, address translation is done completely by hardware, in parallel with cache
accesses, with no additional cycles incurred.
The 750GX MMU provides independent 8-entry BAT arrays for instructions and data that maintain address
translations for blocks of memory. These entries define blocks that can vary from 128 KB to 256 MB. The
BAT arrays are maintained by system software. Instructions and data share the same virtual address model,
but could operate in separate segment spaces.
The PowerPC 750GX MMU and exception model support demand-paged virtual memory. Virtual memory
management permits execution of programs larger than the size of physical memory. Demand-paged implies
that individual pages for data and instructions are loaded into physical memory from the system disk only
when they are required by an executing program. Infrequently used pages in memory are returned to disk or
discarded if they have not been modified.
The hashed page table is a fixed-sized data structure
1
that contains 8-byte page table entries (PTEs), which
define the mapping between virtual pages and physical pages. The page table size is a power of two and is
boundary aligned in memory based on the size of the table. The page table contains a number of page-table-
entry groups (PTEGs). Since a PTEG contains eight PTEs of eight bytes each, each PTEG is 64 bytes long.
PTEG addresses are entry points for table-search operations. A given page translation can be found in one of
two possible PTEGs. The size and location in memory of the page table is defined in the SDR1 register.
Setting MSR[IR] enables instruction address translations and setting MSR[DR] enables data address transla-
tions. If the bit is cleared, the respective effective address is used as the physical address.
1. Size should be determined by the amount of physical memory available to the system.