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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
PowerPC 750GX Overview
Page 46 of 377
gx_01.fm.(1.2)
March 27,2006
– Translation-lookaside-buffer management instructions
These categories do not indicate the execution unit that executes a particular instruction or group of instruc-
tions.
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on
single-precision (one word) and double-precision (two words) floating-point operands. The PowerPC Archi-
tecture uses instructions that are four bytes long and word-aligned. It provides for integer byte, half-word, and
word operand loads and stores between memory and a set of 32 GPRs. It also provides for single and
double-precision loads and stores between memory and a set of 32 Floating Point Registers (FPRs).
Computational instructions do not access memory. To use a memory operand in a computation and then
modify the same or another memory location, the memory contents must be loaded into a register, modified,
and then written back to the target location using three or more instructions.
PowerPC processors follow the program flow when they are in the normal execution state; however, the flow
of instructions can be interrupted directly by the execution of an instruction or by an asynchronous event.
Either type of exception will cause the associated exception handler to be invoked.
Effective address computations for both data and instruction accesses use 32-bit signed two’s complement
binary arithmetic. A carry from bit 0 and overflow are ignored.