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7.2 CPU Clock and Peripheral Function Clock ................................................................................................ 47
7.2.1 CPU Clock and BCLK ........................................................................................................................ 47
7.2.2 Peripheral Function Clock ..................................................................................................................47
7.3 Clock Output Function ...............................................................................................................................47
7.4 Power Control ............................................................................................................................................48
7.4.1 Normal Operation Mode.....................................................................................................................48
7.4.2 Wait Mode .......................................................................................................................................... 50
7.4.3 Stop Mode..........................................................................................................................................52
7.5 Oscillation Stop and Re-oscillation Detection Function ............................................................................. 57
7.5.1 Operation When CM27 Bit = 0 (Oscillation Stop Detection Reset) .................................................... 57
7.5.2 Operation When CM27 Bit = 1 (Oscillation Stop, Re-oscillation Detection Interrupt) ........................ 57
7.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function ..................................................58
8. Protection ............................................................................................................................ 59
9. Interrupt ............................................................................................................................... 60
9.1 Type of Interrupts .......................................................................................................................................60
9.2 Software Interrupts .....................................................................................................................................61
9.2.1 Undefined Instruction Interrupt...........................................................................................................61
9.2.2 Overflow Interrupt ..............................................................................................................................61
9.2.3 BRK Interrupt .....................................................................................................................................61
9.2.4 INT Instruction Interrupt ..................................................................................................................... 61
9.3 Hardware Interrupts ...................................................................................................................................62
9.3.1 Special Interrupts ............................................................................................................................... 62
9.3.2 Peripheral Function Interrupts............................................................................................................62
9.4 Interrupts and Interrupt Vector ...................................................................................................................63
9.4.1 Fixed Vector Tables............................................................................................................................63
9.4.2 Relocatable Vector Tables .................................................................................................................63
9.5 Interrupt Control .........................................................................................................................................65
9.5.1 I Flag .................................................................................................................................................. 67
9.5.2 IR Bit ..................................................................................................................................................67
9.5.3 ILVL2 to ILVL0 Bits and IPL ............................................................................................................... 67
9.5.4 Interrupt Sequence ............................................................................................................................68
9.5.5 Interrupt Response Time.................................................................................................................... 69
9.5.6 Variation of IPL when Interrupt Request is Accepted ......................................................................... 69
9.5.7 Saving Registers ................................................................................................................................70
9.5.8 Returning from an Interrupt Routine ..................................................................................................71
9.5.9 Interrupt Priority .................................................................................................................................71
9.5.10 Interrupt Priority Resolution Circuit .................................................................................................. 71
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9.6 INT Interrupt ...............................................................................................................................................73
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9.7 NMI Interrupt .............................................................................................................................................. 77
9.8 Key Input Interrupt .....................................................................................................................................77
9.9 CAN0/1 Wake-up Interrupt .........................................................................................................................77
9.10 Address Match Interrupt ...........................................................................................................................78
10. Watchdog Timer ................................................................................................................ 80
10.1 Count Source Protective Mode ................................................................................................................ 81