Patton electronic 2616RC Switch User Manual


 
WAN Circuit Configuration—Modify 297
Models 2616RC, 3096RC & 3196RC Admin Reference Guide 20 • T1/E1 Link
Line Interface Settings
This portion of the WAN Circuit Configuration window contains information described in the
following sections.
Circuit ID (dsx1CircuitIdentifier)
This variable contains the transmission vendor’s circuit identifier, for the purpose of
facilitating troubleshooting.
Line Type (dsx1LineType)
This variable indicates the type of DS1 Line implemented on this circuit. The type of circuit affects the num-
ber of bits per second that the circuit can reasonably carry, as well as the interpretation of the usage and error
statistics. The values, in sequence, are:
other(1)—Link is disabled
dsx1ESF(2)—Extended Superframe DS1
dsx1D4(3)—AT&T D4 format DS1
dsx1E1(4)—Based on CCITT/ITU G.704 without CRC (Cyclical Redundancy Check)
dsx1E1-CRC(5)—Based on CCITT/ITU G.704 with CRC (Cyclical Redundancy Check)
dsx1E1-MF(6)—Based on CCIT/ITU G.704 without CRC (bit oriented signaling)
dsx1E1-CRC-MF(7)—Based on CCIT/ITU G.704 with CRC (bit oriented signaling)
dsx1E1-Transparent(8)—Based on CCIT/ITU G.703 without CRC (Cyclical Redundancy Check)
Line Coding (dsx1LineCoding)
This variable describes the type of Zero Code Suppression used on the link, which in turn affects a number of
its characteristics.
dsx1JBZS(1)—Jammed Bit Zero Suppression, in which the AT&T specification of at least one pulse every
8 bit periods is literally implemented by forcing a pulse in bit 8 of each channel. Thus, only seven bits per
channel, or 1.344 Mbps, is available for data. This feature is not currently implemented.
dsx1B8ZS(2)—The use of a specified pattern of normal bits and bipolar violations which are used to
replace a sequence of eight zero bits. The most common coding for T1 circuits.
dsx1HDB3(3)—This line coding is used with most E1 circuits today.
dsx1ZBTSI(4)—May use
dsx1ZBTSI
, or Zero Byte Time Slot Interchange. This feature is not currently
implemented.
dsx1AMI(5)—Refers to a mode wherein no zero code suppression is present and the line encoding does not
solve the problem directly. In this application, the higher layer must provide data which meets or exceeds
the pulse density requirements, such as inverting HDLC data.
other(6)—This feature is not currently supported.