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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR
3-58
UNDEFINED INSTRUCTION
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The
instruction format is shown in Figure 3-28.
31 27
Cond
28 25 24
011
xxxxxxxxxxxxxxxxxxxx
1
xxxx
543 0
Figure 3-28. Undefined Instruction
If the condition is true, the undefined instruction trap will be taken.
Note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be
present, and all coprocessors must refuse to accept it by driving CPA and CPB HIGH.
INSTRUCTION CYCLE TIMES
This instruction takes 2S + 1I + 1N cycles, where S, N and I are defined as sequential (S-cycle), non-sequential (N-
cycle), and internal (I-cycle).
ASSEMBLER SYNTAX
The assembler has no mnemonics for generating this instruction. If it is adopted in the future for some specified
use, suitable mnemonics will be added to the assembler. Until such time, this instruction must not be used.