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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR
3-8
ASSEMBLER SYNTAX
Items in “{}” are optional. Items in “<>” must be present.
B{L}{cond} <expression>
{L}
Used to request the Branch with Link form of the instruction.
If absent, R14 will not be affected by the instruction.
{cond}
A two-character mnemonic as shown in Table 3-2.
If absent then AL (ALways) will be used.
<expression>
The destination. The assembler calculates the offset
Examples
here BAL here ; Assembles to 0xEAFFFFFE (note effect of PC offset).
B there ; Always condition used as default.
CMP R1,#0 ; Compare R1 with zero and branch to fred
if R1 was zero, otherwise continue.
BEQ fred ; Continue to next instruction.
BL sub+ROM ; Call subroutine at computed address.
ADDS R1,#1 ; Add 1 to register 1, setting CPSR flags
on the result then call subroutine if
BLCC sub ; the C flag is clear, which will be the
case unless R1 held 0xFFFFFFFF.