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S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL
2-5
The THUMB State Register Set
The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight
general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR),
and the CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for
each privileged mode. This is shown in Figure 2-4.
R0
R1
R2
R3
R4
R5
R6
R7
LR
SP
PC
System & User
FIQ
Supervisor IRQAbort Undefined
THUMB State General Registers and Program Counter
THUMB State Program Status Registers
CPSR CPSR
SPSR_
fiq
CPSR
SPSR_
svc
CPSR
SPSR_
abt
CPSR
SPSR_
irq
CPSR
SPSR_
und
= banked register
LR_
fiq
R0
R1
R2
R3
R4
R5
R6
R7
SP_
fiq
PC
LR_
svc
R0
R1
R2
R3
R4
R5
R6
R7
SP_
svc
PC
LR_
und
R0
R1
R2
R3
R4
R5
R6
R7
SP_
und
PC
LR_
fiq
R0
R1
R2
R3
R4
R5
R6
R7
SP_
fiq
PC
LR_
abt
R0
R1
R2
R3
R4
R5
R6
R7
SP_
abt
PC
Figure 2-4. Register Organization in THUMB state