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PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR
2-14
Exception Priorities
When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are
handled:
Highest priority:
1. Reset
2. Data abort
3. FIQ
4. IRQ
5. Prefetch abort
Lowest priority:
6. Undefined Instruction, Software interrupt.
Not All Exceptions Can Occur at Once:
Undefined Instruction and Software Interrupt are mutually exclusive, since they each correspond to particular (non-
overlapping) decodings of the current instruction.
If a data abort occurs at the same time as a FIQ, and FIQs are enabled (ie the CPSR's F flag is clear), ARM920T
enters the data abort handler and then immediately proceeds to the FIQ vector. A normal return from FIQ will
cause the data abort handler to resume execution. Placing data abort at a higher priority than FIQ is necessary to
ensure that the transfer error does not escape detection. The time for this exception entry should be added to
worst-case FIQ latency calculations.