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I/O PORTS S3C2440A RISC MICROPROCESSOR
9-32
EINTMASK(External Interrupt Mask Register)
Register Address R/W Description Reset Value
EINTMASK 0x560000a4 R/W External interupt mask Register 0x000fffff
EINTMASK Bit Description
EINT23 [23] 0 = enable interrupt 1= masked
EINT22 [22] 0 = enable interrupt 1= masked
EINT21 [21] 0 = enable interrupt 1= masked
EINT20 [20] 0 = enable interrupt 1= masked
EINT19 [19] 0 = enable interrupt 1= masked
EINT18 [18] 0 = enable interrupt 1= masked
EINT17 [17] 0 = enable interrupt 1= masked
EINT16 [16] 0 = enable interrupt 1= masked
EINT15 [15] 0 = enable interrupt 1= masked
EINT14 [14] 0 = enable interrupt 1= masked
EINT13 [13] 0 = enable interrupt 1= masked
EINT12 [12] 0 = enable interrupt 1= masked
EINT11 [11] 0 = enable interrupt 1= masked
EINT10 [10] 0 = enable interrupt 1= masked
EINT9 [9] 0 = enable interrupt 1= masked
EINT8 [8] 0 = enable interrupt 1= masked
EINT7 [7] 0 = enable interrupt 1= masked
EINT6 [6] 0 = enable interrupt 1= masked
EINT5 [5] 0 = enable interrupt 1= masked
EINT4 [4] 0 = enable interrupt 1= masked
Reserved [3:0] Reserved