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S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL
2-9
Table 2-1. PSR Mode Bit Values
M[4:0] Mode Visible THUMB state registers Visible ARM state registers
10000 User R7..R0,
LR, SP
PC, CPSR
R14..R0,
PC, CPSR
10001 FIQ R7..R0,
LR_fiq, SP_fiq
PC, CPSR, SPSR_fiq
R7..R0,
R14_fiq..R8_fiq,
PC, CPSR, SPSR_fiq
10010 IRQ R7..R0,
LR_irq, SP_irq
PC, CPSR, SPSR_irq
R12..R0,
R14_irq, R13_irq,
PC, CPSR, SPSR_irq
10011 Supervisor R7..R0,
LR_svc, SP_svc,
PC, CPSR, SPSR_svc
R12..R0,
R14_svc, R13_svc,
PC, CPSR, SPSR_svc
10111 Abort R7..R0,
LR_abt, SP_abt,
PC, CPSR, SPSR_abt
R12..R0,
R14_abt, R13_abt,
PC, CPSR, SPSR_abt
11011 Undefined R7..R0
LR_und, SP_und,
PC, CPSR, SPSR_und
R12..R0,
R14_und, R13_und,
PC, CPSR
11111 System R7..R0,
LR, SP
PC, CPSR
R14..R0,
PC, CPSR
Reserved bits The remaining bits in the PSR's are reserved. While changing a PSR's flag or control bits,
you must ensure that these unused bits are not altered. Also, your program should not rely
on them containing specific values, since in future processors they may read as one or
zero.