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S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET
4-25
INSTRUCTION CYCLE TIMES
All instructions in this format have an equivalent ARM instruction as shown in Table 4-11. The instruction cycle
times for the THUMB instruction are identical to that of the equivalent ARM instruction.
EXAMPLES
STRH R6, [R1, #56] ; Store the lower 16 bits of R4 at the address formed by
adding 56 R1. Note that the THUMB opcode will contain
28 as the Offset5 value.
LDRH R4, [R7, #4] ; Load into R4 the halfword found at the address formed by
adding 4 to R7. Note that the THUMB opcode will contain
2 as the Offset5 value.