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S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA
27-11
nRESET
XTIpll or
EXTCLK
VCO
output
MCU operates by XTIpll
or EXTCLK clcok.
Clock
Disable
tPLL
FCLK is new frequency.
Power
PLL can operate after OM[3:2] is latched.
PLL is configured by S/W first time.
VCO is adapted to new clock frequency.
FCLK
...
...
...
tRST2RUN
Figure 27-7 Power-On Oscillation Setting Timing Diagram