Filter
Top Products
S3C2440A RISC MICROPROCESSOR BUS PRIORITIES
25-1
25 BUS PRIORITIES
OVERVIEW
The bus arbitration logic determines the priorities of bus masters. It supports a combination of rotation priority
mode and fixed priority mode.
BUS PRIORITY MAP
The S3C2440A holds 13 bus masters. They include DRAM refresh controller, LCD_DMA, CAMIF DMA, DMA0,
DMA1, DMA2, DMA3, USB_HOST_DMA, EXT_BUS_MASTER, Test interface controller (TIC) and ARM920T. The
following list shows the priorities among these bus masters after a reset:
1. DRAM refresh controller
2. LCD_DMA
3. CAMIF codec DMA
4. CAMIF preview DMA
5. DMA0
6. DMA1
7. DMA2
8. DMA3
9. USB host DMA
10. External bus master
11. TIC
12. ARM920T
13. Reserved
Among these bus masters, the four DMAs (DMA0, DMA1, DMA2 and DMA3) operate under rotation priority, while
the others run under fixed priority.