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ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR
27-20
HCLK
nGCSx
nOE
Tacc = 6cycle
nWait
DATA
ADDR
Tacs
Tacs
delayed
tRC
NOTE:
The status of nWait is checked at (Tacc-1) cycle.
sampling nWait
Figure 27-16 External nWAIT READ Timing Diagram
(Tacs=0, Tcos=0, Tacc=6, Toch=0, Tcah=0, PMC=0, ST=0)
HCLK
nGCSx
nWE
DATA
ADDR
tRDD
tRDD
Tacc >= 2cycle
nWait
tWS
tWH
Figure 27-17 External nWAIT WRITE Timing Diagram
(Tacs=0, Tcos=0, Tacc=4, Toch=0, Tcah=0, PMC=0, ST=0)