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S3C2440A RISC MICROPROCESSOR DMA
8-3
EXTERNAL DMA DREQ/DACK PROTOCOL
There are three types of external DMA request/acknowledge protocols (Single service Demand, Single service
Handshake and Whole service Handshake mode). Each type defines how the signals like DMA request and
acknowledge are related to these protocols.
Basic DMA Timing
The DMA service means performing paired Reads and Writes cycles during DMA operation, which can make one
DMA operation. Figure 8-1 shows the basic Timing in the DMA operation of the S3C2440A.
- The setup time and the delay time of XnXDREQ and XnXDACK are the same in all the modes.
- If the completion of XnXDREQ meets its setup time, it is synchronized twice and then XnXDACK is
asserted.
- After assertion of XnXDACK, DMA requests the bus and if it gets the bus it performs its operations.
XnXDACK is de-asserted when DMA operation is completed.
XSCLK
9.3ns Setup
9.3ns Setup
6.8ns Delay
6.6ns Delay
Read Write
Min. 2XSCLK
XnXDREQ
XnXDACK
Min. 3XSCLK
Figure 8-1. Basic DMA Timing Diagram