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S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE
23-22
PREVIEW DMA CONTROL REGISTER
Register Address R/W Description Reset Value
CIPRCTRL 0x4F000080 RW Preview DMA control related 0
CIPRCTRL Bit Description Initial State
RGBburst1_Pr [23:19] Main burst length for preview RGB frames 0
RGBburst2_Pr [18:14] Remained burst length for preview RGB frames 0
LastIRQEn_Pr [2]
0 = Normal
1 = Enable last IRQ at the end of frame capture.
(This bit is cleared automatically.)
0
NOTE: All burst lengths must be one of the 2, 4, 8, 16.
Example 1: Target image size: QCIF for RGB 32-bit format (horizontal width = 176 pixels. 1 pixel = 1 word)
176 pixel = 176 word.
176 % 16 = 0 → main burst = 16, remained burst = 16
Example 2: Target image size: VGA for RGB 16-bit format (horizontal width = 640 pixels. 2 pixel = 1 word)
640 / 2 = 320 word
160 % 16 = 0 → main burst = 16, remained burst = 16
PREVIEW PRE-SCALER CONTROL REGISTER 1
Register Address R/W Description Reset Value
CIPRSCPRERATIO 0x4F000084 RW Preview pre-scaler ratio control 0
CIPRSCPRERATIO Bit Description Initial State
SHfactor_Pr [31:28] Shift factor for preview pre-scaler 0
PreHorRatio_Pr [22:16] Horizontal ratio of preview pre-scaler 0
PreVerRatio_Pr [6:0] Vertical ratio of preview pre-scaler 0