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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET
3-17
ASSEMBLER SYNTAX
•
••
• MOV,MVN (single operand instructions).
<opcode>{cond}{S} Rd,<Op2>
•
••
• CMP,CMN,TEQ,TST (instructions which do not produce a result).
<opcode>{cond} Rn,<Op2>
•
••
• AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC
<opcode>{cond}{S} Rd,Rn,<Op2>
where:
<Op2> Rm{,<shift>} or,<#expression>
{cond} A two-character condition mnemonic. See Table 3-2.
{S} Set condition codes if S present (implied for CMP, CMN, TEQ, TST).
Rd, Rn and Rm Expressions evaluating to a register number.
<#expression> If this is used, the assembler will attempt to generate a shifted immediate 8-bit field to
match the expression. If this is impossible, it will give an error.
<shift> <Shiftname> <register> or <shiftname> #expression, or RRX (rotate right one bit with
extend).
<shiftname>s ASL, LSL, LSR, ASR, ROR. (ASL is a synonym for LSL, they assemble to the same
code.)
EXAMPLES
ADDEQ R2,R4,R5 ; If the Z flag is set make R2:=R4+R5
TEQS R4,#3 ; Test R4 for equality with 3.
; (The S is in fact redundant as the
; assembler inserts it automatically.)
SUB R4,R5,R7,LSR R2 ; Logical right shift R7 by the number in
; the bottom byte of R2, subtract result
; from R5, and put the answer into R4.
MOV PC,R14 ; Return from subroutine.
MOVS PC,R14 ; Return from exception and restore CPSR
; from SPSR_mode.