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UART S3C2440A RISC MICROPROCESSOR
11-2
BLOCK DIAGRAM
Buad-rate
Generator
Control
Unit
Transmitter
Receiver
Peripheral BUS
TXDn
Clock Source
(PCLK, FCLK/n,UEXTCLK)
RXDn
Transmit FIFO Register
(FIFO mode)
Transmit Holding Register
(Non-FIFO mode)
Receive FIFO Register
(FIFO mode)
Receive Holding Register
(Non-FIFO mode only)
In FIFO mode, all 64 Byte of Buffer register are used as FIFO register.
In non-FIFO mode, only 1 Byte of Buffer register is used as Holding register.
Transmit Shifter
Transmit Buffer
Register(64 Byte)
Receive Shifter
Receive Buffer
Register(64 Byte)
Figure 11-1 UART Block Diagram (with FIFO)