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DMA S3C2440A RISC MICROPROCESSOR
8-6
EXAMPLES
Single service in Demand Mode with Unit Transfer Size
The assertion of XnXDREQ will be a need for every unit transfer (Single service mode). The operation continues
while the XnXDREQ is asserted (Demand mode), and one pair of Read and Write (Single transfer size) is
performed.
XSCLK
XnXDREQ
XnXDACK
XSCLK
XnXDREQ
XnXDACK
Read Write Read Write
Double synch
Figure 8-4. Single service in Demand Mode with Unit Transfer Size
Single service in Handshake Mode with Unit Transfer Size
XnXDREQ
XnXDACK
XSCLK
Read Write
Read Write
2cycles
Double synch
Figure 8-5. Single service in Handshake Mode with Unit Transfer Size
Whole service in Handshake Mode with Unit Transfer Size
XSCLK
XnXDREQ
XnXDACK
Read Write Read Write Read Write
2cycles 2cycles3 cycles
Double synch
Figure 8-6. Whole service in Handshake Mode with Unit Transfer Size