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THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR
4-2
FORMAT SUMMARY
The THUMB instruction set formats are shown in the following figure.
Move Shifted register
00
0
000
000
000
1
0
0
010
0
0
0
0
0
1
11
1
1
1
1
00
000
1
1
1
1
11
1
1
0
L
0
1
1
1111
1111
1111
1
1
000
0
11
11
00
10
0
L
10R
110
10SP
1L
L
S
H
0
0
1BL
01H
01 B
001
11IOp
Op
Op
Op
Op
L0
S1
Offset5 Rs Rd
Rn/offset3
Rd
Rs Rd
Offset8
Rs
Rd/Hd
Rd
H1 H2 Rs/Hs
Rd
Word8
Rd
RbRo
Ro Rb
Rd
Offset5 Rb Rd
Rb RdOffset5
Rd
Rd
Word8
Word8
SWord7
Rb
Cond
Rlist
Rlist
Softset8
Value8
Offset11
Offset
Add/subtract
Move/compare/add/
subtract immediate
ALU operations
Hi register operations
/branch exchange
PC-relative load
Load/store with register
offset
Load/store with immediate
offset
Load/store sign-extended
byte/halfword
Load/store halfword
SP-relative load/store
Load address
Add offset to stack pointer
Push/pop register
Multiple load/store
Conditional branch
Software interrupt
Unconditional branch
Long branch with link
151413121110987654 2310
151413121110987654 2310
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Figure 4-1. THUMB Instruction Set Formats