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S3C2440A RISC MICROPROCESSOR DMA
8-5
Transfer Size
- There are two different transfer sizes; unit and Burst 4.
- DMA holds the bus firmly during the transfer of the chunk of data. Thus, other bus masters cannot get the
bus.
Burst 4 Transfer Size
There will be four sequential Reads and Writes performed in the Burst 4 Transfer respectively.
Note
Unit Transfer size: One read and one write is performed.
XSCLK
XnXDREQ
XnXDACK
Read Read Read Write Write WriteRead Write
3 cycles
Double synch
Figure 8-3. Burst 4 Transfer Size