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S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE
23-20
CODEC STATUS REGISTER
Register Address R/W Description Reset Value
CICOSTATUS 0x4F000064 R Codec path status 0
CICOSTATUS Bit Description Initial State
OvFiY_Co [31] Overflow state of codec source FIFO Y 0
OvFiCb_Co [30] Overflow state of codec source FIFO Cb 0
OvFiCr_Co [29] Overflow state of codec source FIFO Cr 0
VSYNC [28]
Camera VSYNC (This bit can be referred by CPU for first SFR
setting. And, it can be seen in the ITU-R BT 656 mode, too)
0
FrameCnt_Co [27:26]
Frame count of codec DMA (This counter value indicates the next
frame number)
0
WinOfstEn_Co [25] Window offset enable status 0
FlipMd_Co [24:23] Flip mode of codec DMA 0
ImgCptEn_CamIf [22] Image capture enable of camera interface 0
ImgCptEn_CoSC [21] Image capture enable of codec path 0
RGB1 START ADDRESS REGISTER
Register Address R/W Description Reset Value
CIPRCLRSA1 0x4F00006C RW RGB 1
st
frame start address for preview DMA 0
CIPRCLRSA1 Bit Description Initial State
CIPRCLRSA1 [31:0] RGB 1
st
frame start address for preview DMA 0
RGB2 START ADDRESS REGISTER
Register Address R/W Description Reset Value
CIPRCLRSA2 0x4F000070 RW RGB 2
nd
frame start address for preview DMA 0
CIPRCLRSA2 Bit Description Initial State
CIPRCLRSA2 [31:0] RGB 2
nd
frame start address for preview DMA
0