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S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER
DEC.13, 2002
5-5
nWAIT PIN OPERATION
If the WAIT bit(WSn bit in BWSCON) corresponding to each memory bank is enabled, the nOE duration should be
prolonged by the external nWAIT pin while the memory bank is active. nWAIT is checked from tacc-1. nOE will be
de-asserted at the next clock after sampling nWAIT is high. The nWE signal have the same relation with nOE.
Tacs
Tcos
Tacc=4
HCLK
ADDR
nGCS
nOE
nWAIT
DATA(R)
Delayed
Sampling nWAIT
Figure 5-2. S3C2440A External nWAIT Timing Diagram (Tacc=4)