Filter
Top Products
S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER
DEC.13, 2002
5-3
FUNCTION DESCRIPTION
BANK0 BUS WIDTH
The data bus of BANK0 (nGCS0) should be configured with a width as one of 16-bit and 32-bit ones. Because the
BANK0 works as the booting ROM bank (map to 0x0000_0000), the bus width of BANK0 should be determined
before the first ROM access, which will depend on the logic level of OM[1:0] at Reset.
OM1 (Operating Mode 1) OM0 (Operating Mode 0) Booting ROM Data width
0 0 Nand Flash Mode
0 1 16-bit
1 0 32-bit
1 1 Test Mode
MEMORY (SROM/SDRAM) ADDRESS PIN CONNECTIONS
MEMORY ADDR. PIN S3C2440A ADDR.
@ 8-bit DATA BUS
S3C2440A ADDR.
@ 16-bit DATA BUS
S3C2440A ADDR.
@ 32-bit DATA BUS
A0 A0 A1 A2
A1 A1 A2 A3
. . . . . . . . . . . .