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CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR
7-14
If the user switches from SLOW mode to Normal mode by disabling SLOW_BIT and MPLL_OFF bit
simultaneously in the CLKSLOW register, the frequency is changed just after the PLL lock time. Figure 7-13
(Please check for the figure number correctly) shows the timing diagram.
Mpll
FCLK
SLOW_BIT
Divided
OSC clock
MPLL_OFF
Hardware lock time
PLL off PLL on
Slow mode enable
It changes to PLL clock
after lock time automatically
Slow mode disable
Figure 7-11. Issuing Exit_from_Slow_mode Command and the Instant PLL_on Command Simultaneously