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S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET
3-39
EXAMPLES
LDRH R1,[R2,-R3]! ; Load R1 from the contents of the halfword address
; contained in R2-R3 (both of which are registers)
; and write back address to R2
STRH R3,[R4,#14] ; Store the halfword in R3 at R14+14 but don't write back.
LDRSB R8,[R2],#-223 ; Load R8 with the sign extended contents of the byte
; address contained in R2 and write back R2-223 to R2.
LDRNESH R11,[R0] ; Conditionally load R11 with the sign extended contents
; of the halfword address contained in R0.
HERE ; Generate PC relative offset to address FRED.
STRH R5, [PC,#(FRED-HERE-8)]; Store the halfword in R5 at address FRED
FRED