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S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT
7-9
NOTE
1. CLKDIVN should be set carefully not to exceed the limit of HCLK and PCLK.
2. If HDIVN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous bus
mode using following instructions(S3C2440 does not support synchronous bus mode).
MMU_SetAsyncBusMode
mrc p15,0,r0,c1,c0,0
orr r0,r0,#R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
If HDIVN is not 0 and the CPU bus mode is the fast bus mode, the CPU will operate by the HCLK. This
feature can be used to change the CPU frequency as a half or more without affecting the HCLK and
PCLK.