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S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET
4-15
EXAMPLES
Hi-Register Operations
ADD PC, R5 ; PC := PC + R5 but don't set the condition codes.
CMP R4, R12 ; Set the condition codes on the result of R4 - R12.
MOV R15, R14 ; Move R14 (LR) into R15 (PC) but don't set the condition
codes, eg. return from subroutine.
Branch and Exchange
; Switch from THUMB to ARM state.
ADR R1,outofTHUMB ; Load address of outofTHUMB into R1.
MOV R11,R1
BX R11 ; Transfer the contents of R11 into the PC.
; Bit 0 of R11 determines whether
; ARM or THUMB state is entered, ie. In this case the
state is ARM.
ALIGN
CODE32
outofTHUMB ; Now processing ARM instructions...
USING R15 AS AN OPERAND
If R15 is used as an operand, the value will be the address of the instruction + 4 with bit 0 cleared. Executing a BX
PC in THUMB state from a non-word aligned address will result in unpredictable execution.