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S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE
20-13
MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER
Register Address R/W Description Reset Value
IICADD 0x54000008 R/W IIC-Bus address register 0xXX
IICADD Bit Description Initial State
Slave address [7:0] 7-bit slave address, latched from the IIC-bus.
When serial output enable = 0 in the IICSTAT, IICADD is
write-enabled. The IICADD value can be read any time,
regardless of the current serial output enable bit (IICSTAT)
setting.
Slave address : [7:1]
Not mapped : [0]
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MULTI-MASTER IIC-BUS TRANSMIT/RECEIVE DATA SHIFT (IICDS) REGISTER
Register Address R/W Description Reset Value
IICDS 0x5400000C R/W IIC-Bus transmit/receive data shift register 0xXX
IICDS Bit Description Initial State
Data shift [7:0] 8-bit data shift register for IIC-bus Tx/Rx operation.
When serial output enable = 1 in the IICSTAT, IICDS is
write-enabled. The IICDS value can be read any time,
regardless of the current serial output enable bit (IICSTAT)
setting.
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