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IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR
21-4
IIS-bus Format (N=8 or 16)
MSB
(1st)
2nd
Bit
N-1th
Bit
LSB
(last)
MSB
(1st)
2nd
Bit
N-1th
Bit
LSB
(last)
MSB
(1st)
LRCK
SCLK
SD
LEFT RIGHT LEFT
MSB-justified Format (N=8 or 16)
2nd
Bit
N-1th
Bit
LSB
(last)
MSB
(1st)
2nd
Bit
N-1th
Bit
LSB
(last)
LRCK
SCLK
SD
LEFT RIGHT
MSB
(1st)
Figure 21-2. IIS-Bus and MSB (Left)-justified Data Interface Formats
SAMPLING FREQUENCY AND MASTER CLOCK
Master clock frequency (PCLK or MPLLin) can be selected by sampling frequency as shown in Table 21-1.
Because Master clock is made by IIS prescaler, the prescaler value and Master clock type (256 or 384fs) should
be determined properly. Serial bit clock frequency type (16/32/48fs) can be selected by the serial bit per channel
and Master clock as shown in Table 21-2.
Table 21-1 CODEC clock (CODECLK = 256 or 384fs)
IISLRCK
(fs)
8.000
KHz
11.025
KHz
16.000
KHz
22.050
KHz
32.000
KHz
44.100
KHz
48.000
KHz
64.000
KHz
88.200
KHz
96.000
KHz
256fs
CODECLK
2.0480 2.8224 4.0960 5.6448 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760
(MHz)
384fs
3.0720 4.2336 6.1440 8.4672 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640
Table 21-2 Usable serial bit clock frequency (IISCLK = 16 or 32 or 48fs)
Serial bit per channel 8-bit 16-bit
Serial clock frequency (IISCLK)
@CODECLK = 256fs 16fs, 32fs 32fs
@CODECLK = 384fs 16fs, 32fs, 48fs 32fs, 48fs