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<unmask > is the decimal, hexadecimal (#H), octal (#Q), or binary (#B)
value of the Condition register bit to be unmasked. (Bits 0, 6, 8, and 9 have
corresponding decimal values of 1, 64, 256, and 512.)
The Event Register The Event register latches transition events from the Condition register as
specified by the Transition Filter. Bits in the Event register are latched and
remain set until the register is cleared by one of the following commands:
STATus:OPERation[:EVENt]?
*CLS
The Enable Register The Enable register specifies which bits in the Event register can generate a
summary bit which is subsequently used to generate a service request. The
digitizer logically ANDs the bits in the Event register with bits in the
Enable register, and ORs the results to obtain a summary bit.
The bits in the Enable register that are to be ANDed with bits in the Event
register are specified (unmasked) with the command:
STATus:OPERation:ENABle <
unmask
>
<unmask > is the decimal, hexadecimal (#H), octal (#Q), or binary (#B)
value of the Enable register bit to be unmasked. (Bits 0, 6, 8, and 9 have
corresponding decimal values of 1, 64, 256, and 512.)
The Enable register is cleared at power-on, by specifying an <unmask >
value of 0, or by executing the STATus:PRESet command.
The Standard Event
Status Group
The Standard Event status group monitors command execution errors,
programming errors, and the power-on state.
The Standard Event
Status Register
The conditions monitored by the Standard Event Status register are
identified below.
76543210
PON unused CME EXE DDE QYE unused OPC
Power-on (PON): Bit 7 is set (1) when an off-to-on transition has occurred.
Command Error (CME): Bit 5 is set (1) when an incorrect command
header is received, or if an un-implemented common command is received.
Execution Error (EXE): Bit 4 is set (1) when a command parameter is
outside its legal range.
170 Understanding the HP E1429 Digitizer Chapter 3