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Device Dependent Error (DDE): Bit 3 is set (1) when an error other than a
command error, execution error, or query error has occurred.
Query Error (QYE): Bit 2 is set (1) when the digitizer output queue is read
and no data is present, or when data in the output queue has been lost.
Operation Complete (OPC): Bit 0 is set (1) when the *OPC command is
received. *OPC is used to indicate when all pending (or previous) digitizer
commands have completed.
Note that bits 7, 5, 4, 3, 2, and 0 have corresponding decimal values of 128,
32, 16, 8, 4, and 1.
Reading the Standard Event Status Register
The settings of the Standard Event Status register can be read with the
command:
*ESR?
The bits are cleared at power-on, or by *ESR? or *CLS.
The Standard Event
Status Enable Register
The Standard Event Status Enable register specifies which bits in the
Standard Event Status register can generate a summary bit which is
subsequently used to generate a service request. The digitizer logically
ANDs the bits in the Event register with bits in the Enable register, and ORs
the results to obtain a summary bit.
The bits in the Enable register that are to be ANDed with bits in the Event
register are specified (unmasked) with the command:
*ESE <
unmask
>
<unmask > is the decimal, hexadecimal (#H), octal (#Q), or binary (#B)
value of the Enable register bit to be unmasked. (Bits 7, 5, 4, 3, 2, and 0
have corresponding decimal values of 128, 32, 16, 8, 4, and 1.)
All unmasked bits in the Enable register can be determined with the
command:
*ESE?
The Standard Event Status Enable register is cleared at power-on, or with an
<unmask > value of 0.
Chapter 3 Understanding the HP E1429 Digitizer 171