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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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10.29 T1/E1/J1 Transmit Flow Diagrams
Figure 10-17. T1/J1 Transmit Flow Diagram
ESCR.4 TESE
TSER
TSIG
HSIE1-3
through
PCPR
TX
ESTORE
Off-Chip
Connection
RDATA
From
T1_rcv_logic
LBCR1.1 PLB
HDLC
Engine
#1
THMS1 H1TC.4
H1TCS1-3
H1TTSBS
HDLC
Engine
#2
THMS2 H2TC.4
H2TCS1-3
H2TTSBS
PCLR1-3
T1 TRANSMIT
FLOW
DIAGRAM
KEY
- PIN
- SELECTOR
- REGISTER
Hardware
Signaling
Estore Mux
Payload
Loopback
HDLC Mux #1
HDLC Mux #2
HDLC FDL #2
HDLC FDL #1
TDATA
TESO
TLINK
H1TC.4
THMS1
FDL Mux
TFDL
Tx FDL
Zero
Stuffer
H2TC.4
THMS2
T1TCR2.5
TZSE
T1TCR1.2
TFDLS
TFDL
BOC
Engine
BOC Mux
BOCC.0 SBOC
Idle Code Mux
Idle
Code
Array
TCICE1-3
Loop
Code
Gen
Loop Code
D4 12th Fs
Yellow
alarm
FPS or
Ft/Fs
insertion
ESF Yellow
Alarm
T1CCR1.2 TFM
T1TCR2.2 TD4YM
T1TCR1.0 TYEL
Per-Channel
Loopback
Software Sig
Software
Sig
Registers
SSIE1-3
F-bit Mux
TFPT T1TCR1.5
To FDL Mux
To ESF Yellow
Mux
To FDL Mux
TLOOP T1CCR1.0