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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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13.11 AC Characteristics: Transmit Side
Table 13-16. AC Characteristics: Transmit Side
(V
DD
= 3.3V ±5%, T
A
= 0°C to +85°C.) (Note 1, Figure 13-17, Figure 13-18, and Figure 13-19)
PARAMETER SYMBOL CONDITIONS MIN TYP (E1) MAX UNITS
488 (E1)
TCLKT Period t
CP
648 (T1)
ns
t
CH
20 0.5 t
CP
TCLKT Pulse Width
t
CL
20 0.5 t
CP
ns
488 (E1)
TDCLKI Period t
LP
648 (T1)
ns
t
LH
20 0.5 t
LP
TDCLKI Pulse Width
t
LL
20 0.5 t
LP
ns
(Note 2) 648
TSYSCLK Period t
SP
(Note 3) 448
ns
20 0.5 t
SP
TSYSCLK Pulse Width t
SP
20 0.5 t
SP
ns
TSYNC or TSSYNC Setup to TCLKT or
TSYSCLK Falling
t
SU
20 ns
TSYNC or TSSYNC Pulse Width t
PW
50 ns
TSERI, TSIG, TDATA, TPOSI, TNEGI
Setup to TCLKT, TSYSCLK, TDCLKI
Falling
t
SU
20 ns
TSERI, TSIG, TDATA Hold from TCLKT
or TSYSCLK Falling
t
HD
20 ns
TPOSI, TNEGI Hold from TDCLKI
Falling
t
HD
20 ns
TCLKT, TDCLKI or TSYSCLK Rise and
Fall Times
t
R
, t
F
25 ns
Delay TCLKO to TPOSO, TNEGO Valid t
DD
50 ns
Delay TCLKT to TESO, UT-UTDO Valid t
D1
50 ns
Delay TCLKT to TCHBLK, TCHCLK,
TSYNC
t
D2
50 ns
Delay TSYSCLK to TCHCLK, TCHBLK t
D3
22 ns
Note 1: Timing parameters in this table are guaranteed by design (GBD).
Note 2: TSYSCLK = 1.544MHz.
Note 3: TSYSCLK = 2.048MHz.