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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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Figure 13-17. Transmit-Side Timing
t
F
t
R
1
TCLKT
TSERI / TSIG /
TDATA
TCHCLK
t
t
CL
t
CH
CP
TSYNC
TSYNC
TLINK
TLCLK
TCHBLK
t
D2
t
D2
t
D2
t
t
t
t
t
t
HD
SU
D2
SU
HD
D1
t
HD
2
5
TESO
t
SU
NOTE 1: TSYNC IS IN THE OUTPUT MODE (IOCR1.1 = 1).
NOTE 2: TSYNC IS IN THE INPUT MODE (IOCR1.1 = 0).
NOTE 3: TSERI IS SAMPLED ON THE FALLING EDGE OF TCLKT WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED.
NOTE 4: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TCLKT WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED.