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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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Register Name:
TR.SSIE1 (E1 Mode)
Register Description:
Software Signaling Insertion Enable 1
Register Address:
08h
Bit # 7 6 5 4 3 2 1 0
Name CH7 CH6 CH5 CH4 CH3 CH2 CH1 UCAW
Default 0 0 0 0 0 0 0 0
Bits 1 – 7: Software Signaling-Insertion Enable for Channels 1 to 7 (CH1 to CH7). These bits determine which
channels are to have signaling inserted from the transmit signaling registers.
0 = do not source signaling data from the TR.TSx registers for this channel
1 = source signaling data from the TR.TSx registers for this channel
Bit 0: Upper CAS Align/Alarm Word (UCAW). Selects the upper CAS align/alarm pattern (0000) to be sourced
from the upper 4 bits of the TS1 register.
0 = do not source the upper CAS align/alarm pattern from the TR.TS1 register
1 = source the upper CAS align/alarm pattern from the TR.TS1 register
Register Name:
TR.SSIE2 (T1 Mode)
Register Description:
Software Signaling-Insertion Enable 2
Register Address:
09h
Bit # 7 6 5 4 3 2 1 0
Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
Default 0 0 0 0 0 0 0 0
Bits 0 – 7: Software Signaling Insertion Enable for Channels 9 to 16 (CH9 to CH16). These bits determine
which channels are to have signaling inserted from the transmit signaling registers.
0 = do not source signaling data from the TR.TSx registers for this channel
1 = source signaling data from the TR.TSx registers for this channel
Register Name:
TR.SSIE2 (E1 Mode)
Register Description:
Software Signaling Insertion Enable 2
Register Address:
09h
Bit # 7 6 5 4 3 2 1 0
Name CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
Default 0 0 0 0 0 0 0 0
Bits 0 – 7: Software Signaling Insertion Enable for Channels 8 to 15 (CH8 to CH15). These bits determine
which channels are to have signaling inserted from the transmit signaling registers.
0 = do not source signaling data from the TR.TSx registers for this channel
1 = source signaling data from the TR.TSx registers for this channel