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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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8 FUNCTIONAL DESCRIPTION
The DS33R11 provides interconnection and mapping functionality between Ethernet packet LANs and T1/E1/J1
WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, packet
arbiter, committed information rate controller (CIR), HDLC/X.86 (LAPS) mapper, SDRAM interface, control ports,
bit error-rate tester (BERT), and integrated T1/E1/J1 transceiver. The packet interface consists of a MII/RMII
Ethernet PHY interface. The Ethernet interface can be configured for 10Mbit/s or 100Mbit/s service. The DS33R11
encapsulates Ethernet traffic with HDLC or X.86 (LAPS) encoding to be transmitted over a T1, E1, or J1 line. The
T1/E1/J1 interface also receives encapsulated Ethernet packets and transmits the extracted packets over the
Ethernet ports. Access is provided to the signals between the serial port and the integrated T1/E1/J1 transceiver.
The Ethernet packet interface supports MII and RMII interfaces, allowing the DSZ33R11 to connect to
commercially available Ethernet PHY and MAC devices. The Ethernet interface can be configured for 10Mbit/s or
100Mbit/s service, in DTE and DCE configurations. The DS33R11 MAC interface rejects frames with bad FCS and
short frames (less than 64 bytes).
Ethernet frames are queued and stored in external 32-bit SDRAM. The DS33R11 SDRAM controller enables
connection to a 128Mb SDRAM without external glue logic, at clock frequencies up to 100MHz. The SDRAM is
used for both the transmit and receive data queues. The receive queue stores data to be sent from the packet
interface to the WAN serial interface. The transmit queue stores data to be sent from the WAN serial interface to
the Ethernet LAN packet interface. The external SDRAM can accommodate up to 8192 frames with a maximum
frame size of 2016 bytes. The sizing of the queues can be adjusted by software. The user can also program high
and low watermarks for each queue that can be used for automatic or manual flow control. The packet data stored
in the SDRAM is encapsulated in HDLC or X.86 (LAPS) to be transmitted over the WAN interface. The device also
provides the capability for bit and packet scrambling.
The WAN interface also receives encapsulated Ethernet packets and transmits the extracted packets over the
Ethernet port. The WAN serial port can operate with a gapped clock, and is designed to be connected to the
integrated T1/E1/J1 transceiver for transmission.
The DS33R11 can be configured through an 8-bit microprocessor interface port. Diagnostic capabilities include
loopbacks, PRBS pattern generation/detection, and 16-bit loop-up/loop-down code generation and detection. The
DS33R11 provides two on-board clock dividers for the system-clock input and reference-clock input for the 802.3
interfaces, further reducing the need for ancillary devices.
The integrated transceiver is a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and
long-haul applications. The transceiver is composed of an LIU, framer, HDLC controllers, and a TDM backplane
interface, and is controlled by the 8-bit parallel port. The transceiver is software compatible with the DS2155 and
DS2156.
The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is responsible
for generating the necessary waveshapes for driving the network and providing the correct source impedance
depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well as CSU line
build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75Ω coax
and 120Ω twisted cables. The receive interface provides network termination and recovers clock and data from the
network. The receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0 to 43dB
or 0 to 12dB for E1 applications and 0 to 30dB or 0 to 36dB for T1 applications. The jitter attenuator removes
phase jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz
MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications) and can be
placed in either transmit or receive data paths. An additional feature of the LIU is a CMI coder/decoder for
interfacing to optical networks.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receive-
side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane
interface section.