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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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12.4 E1 Mode
Figure 12-20. Receive-Side Timing
FRAME#
1
23456789101112131415161
RSYNC
1
RSYNC
RFSYNC
2
NOTE 1: RSYNC IN FRAME MODE (TR.IOCR1.5 = 0).
NOTE 2: RSYNC IN MULTIFRAME MODE (TR.IOCR1.5 = 1).
NOTE 3: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME.
Figure 12-21. Receive-Side Boundary Timing (with Elastic Store Disabled)
CHANNEL 32
CHANNEL 1 CHANNEL 2
CHANNEL 32
CHANNEL 1 CHANNEL 2
RCLKO
RSERO
RSYNC
RFSYNC
RSIG
RCHCLK
RCHBLK
1
CD A
LSB
MSB
AB
Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8
B
Note 4
NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 2: SHOWN IS A RNAF FRAME BOUNDARY.
NOTE 3: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.