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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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10.17.4 FIFO Information...................................................................................................................................96
10.17.5 Receive Packet-Bytes Available...........................................................................................................96
10.18 LEGACY FDL SUPPORT (T1 MODE) ............................................................................................... 97
10.18.1 Overview ...............................................................................................................................................97
10.18.2 Receive Section....................................................................................................................................97
10.18.3 Transmit Section ...................................................................................................................................98
10.19 D4/SLC-96 OPERATION................................................................................................................ 98
10.20 PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION............................................ 99
10.21 LINE INTERFACE UNIT (LIU)......................................................................................................... 100
10.21.1 LIU Operation......................................................................................................................................100
10.21.2 Receiver..............................................................................................................................................100
10.21.3 Transmitter..........................................................................................................................................102
10.22 MCLK PRESCALER ..................................................................................................................... 103
10.23 JITTER ATTENUATOR................................................................................................................... 103
10.24 CMI (CODE MARK INVERSION) OPTION........................................................................................ 103
10.25 RECOMMENDED CIRCUITS ........................................................................................................... 104
10.26 T1/E1/J1 TRANSCEIVER BERT FUNCTION ........................................................................... 108
10.26.1 BERT Status .......................................................................................................................................108
10.26.2 BERT Mapping....................................................................................................................................108
10.26.3 BERT Repetitive Pattern Set ..............................................................................................................110
10.26.4 BERT Bit Counter................................................................................................................................110
10.26.5 BERT Error Counter............................................................................................................................110
10.26.6 BERT Alternating Word-Count Rate...................................................................................................110
10.27 PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY) ........................................................... 111
10.27.1 Number-of-Errors Registers................................................................................................................111
10.28 PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER..................................................................... 112
10.29 FRACTIONAL T1/E1 SUPPORT ..................................................................................................... 112
10.30 T1/E1/J1 TRANSMIT FLOW DIAGRAMS......................................................................................... 113
11 DEVICE REGISTERS..................................................................................................................... 117
11.1 REGISTER BIT MAPS ................................................................................................................... 118
11.1.1 Global Ethernet Mapper Register Bit Map..........................................................................................118
11.1.2 Arbiter Register Bit Map......................................................................................................................119
11.1.3 BERT Register Bit Map.......................................................................................................................119
11.1.4 Serial Interface Register Bit Map ........................................................................................................120
11.1.5 Ethernet Interface Register Bit Map....................................................................................................122
11.1.6 MAC Register Bit Map ........................................................................................................................123
11.2 GLOBAL REGISTER DEFINITIONS FOR ETHERNET MAPPER............................................................ 134
11.3 ARBITER REGISTERS ................................................................................................................... 143
11.3.1 Arbiter Register Bit Descriptions.........................................................................................................143
11.4 BERT REGISTERS ...................................................................................................................... 144
11.5 SERIAL INTERFACE REGISTERS.................................................................................................... 151
11.5.1 Serial Interface Transmit and Common Registers..............................................................................151
11.5.2 Serial Interface Transmit Register Bit Descriptions ............................................................................151
11.5.3 Transmit HDLC Processor Registers..................................................................................................152
11.5.4 X.86 Registers.....................................................................................................................................159
11.5.5 Receive Serial Interface......................................................................................................................161
11.6 ETHERNET INTERFACE REGISTERS .............................................................................................. 174
11.6.1 Ethernet Interface Register Bit Descriptions.......................................................................................174
11.6.2 MAC Registers....................................................................................................................................186
11.7 T1/E1/J1 TRANSCEIVER REGISTERS ........................................................................................... 201
11.7.1 Number-of-Errors Left Register...........................................................................................................299
12 FUNCTIONAL TIMING................................................................................................................... 300
12.1 FUNCTIONAL SERIAL I/O TIMING .................................................................................................. 300
12.2 MII AND RMII INTERFACES .......................................................................................................... 301
12.3 TRANSCEIVER T1 MODE FUNCTIONAL TIMING .............................................................................. 303