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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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Figure 9-1. Clocking for the DS33R11
TTIP
TRING
RTIP
RRING
SYSCLKI
REF_CLKO
RX_CLK
REF_CLK
TX_CLK
MDC
MCLK
XTALD
8XCLK
BPCLK
TDCLKI
TDCLKO
TSYSCLK
TCHBLK
TCHCLK
TCLKT
TCLKE
TDEN
JTCLK2
RDCLKI
RDCLKO
RSYSCL
K
RCHBL
K
RCHCL
K
RCLKO
RCLKI
RDEN
TRANSMIT
LIU
RECEIVE
LIU
TRANSMIT
FRAMER
RECEIVIE
FRAMER
ETHERNET MAC
μP Port
SDRAM PORT
SDCL
K
JTCLK1
ARBITER
CIR
CONTROLLER
PACKET
HDLC/X.86
PACKET
HDLC/X.86
ETHERNET
MAPPER
T1/E1/J1
TRANSCEIVER
TRANSMIT
SERIAL
PORT
RECEIVE
SERIAL
PORT
JTAG2 JTAG1
CLAD
MUX
MUX
CLAD
BERT
BERT
HDLC
HDLC
NOTE THAT THE CLOCKING OPTIONS OF THE INTEGRATED T1/E1/J1 TANSCEIVER ARE DISCUSSED IN SECTION 10.1.