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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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Table 10-1. T1/E1/J1 Transmit Clock Source
TCSS1 TCSS0 TRANSMIT CLOCK SOURCE
0 0 The TCLKT pin (C) is always the source of transmit clock.
0 1
Switch to the recovered clock (B) when the signal at the TCLKT pin
fails to transition after one channel time.
1 0
Use the scaled signal (A) derived from MCLK as the transmit clock.
The TCLKT pin is ignored.
1 1
Use the recovered clock (B) as the transmit clock. The TCLKT pin is
ignored.
10.2 Per-Channel Operation
Some of the features described in the data sheet that operate on a per-channel basis use a special method for
channel selection. There are five registers involved: per-channel pointer register (TR.PCPR) and per-channel data
registers 1–4 (TR.PCDR1–4). The user selects which function or functions are to be applied on a per-channel
basis by setting the appropriate bit(s) in the TR.PCPR register. The user then writes to the TR.PCDR registers to
select the channels for that function. The following is an example of mapping the transmit and receive BERT
function to channels 9–12, 20, and 21.
Write 11h to TR.PCPR
Write 00h to TR.PCDR1
Write 0fh to TR.PCDR2
Write 18h to TR.PCDR3
Write 00h to TR.PCDR4
The user may write to the TR.PCDR1-4 with multiple functions in the TR.PCPR register selected, but can only read
the values from the TR.PCDR1-4 registers for a single function at a time. More information about how to use these
per-channel features can be found in the
TR.PCPR register.
10.3 T1/E1/J1 Transceiver Interrupts
Various alarms, conditions, and events in the T1/E1/J1 transceiver can cause interrupts. For simplicity, these are
all referred to as events in this explanation. All status registers can be programmed to produce interrupts. Each
status register has an associated interrupt mask register. For example, TR.SR1 (status register 1) has an interrupt
control register called TR.IMR1 (interrupt mask register 1). Status registers are the only sources of interrupts in the
device. On power-up, all writeable registers of the T1/E1/J1 transceiver are automatically cleared. Since bits in the
TR.IMRx registers have to be set = 1 to allow a particular event to cause an interrupt, no interrupts can occur until
the host selects which events are to product interrupts. Since there are potentially many sources of interrupts on
the device, several features are available to help sort out and identify which event is causing an interrupt. When an
interrupt occurs, the host should first read the TR.IIR1 and TR.IIR2 registers (interrupt information registers) to
identify which status register (or registers) is producing the interrupt. Once that is determined, the individual status
register or registers can be examined to determine the exact source.
Once an interrupt has occurred, the interrupt handler routine should set the INTDIS bit (TR.CCR3.6) to stop further
activity on the interrupt pin. After all interrupts have been determined and processed, the interrupt hander routine
should re-enable interrupts by setting the INTDIS bit = 0.
Note that the integrated Ethernet Mapper also generates interrupts, as discussed in Section 9.6.