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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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9.3 Initialization and Configuration
EXAMPLE DEVICE INITIALIZATION SEQUENCE:
STEP 1: Apply 3.3V supplies, then apply 1.8V supplies.
STEP 2: Reset the integrated Ethernet Mapper by pulling the RST pin low or by using the software reset bits
outlined in Section
9.2. Clear all reset bits. Allow 5ms for the reset recovery.
STEP 3: Reset the integrated T1/E1/J1 Transceiver through hardware using the TSTRST pin or through software
using the SFTRST function in the master mode register.
STEP 4: The LIRST (TR.LIC2.6) should be toggled from 0 to 1 to reset the line interface circuitry. Allow 40ms for
the reset recovery.
STEP 5: Check the Ethernet Mapper Device ID in the
GL.IDRL and GL.IDRH registers.
STEP 6: Check the T1/E1/J1 Transceiver Device ID in the TR.IDR register.
STEP 7: Configure the system clocks. Allow the clock system to properly adjust.
STEP 8: Initialize the entire remainder of the register space with 00h (or otherwise if specifically noted in the
register’s definition), including the reserved bits and reserved register locations.
STEP 9: Write FFFFFFFFh to the MAC indirect addresses 010Ch through 010Fh.
STEP 10: Setup connection in the GL.CON1 register.
STEP 11: Configure the Serial Port register space as needed.
STEP 12: Configure the Ethernet Port register space as needed.
STEP 13: Configure the Ethernet MAC indirect registers as needed.
STEP 14: Configure the T1/E1/J1 Framer as needed.
STEP 15: Configure the T1/E1/J1 LIU as needed.
STEP 16: Configure the external Ethernet PHY through the MDIO interface.
STEP 17: Clear all counters and latched status bits.
STEP 18: Set the queue size in the Arbiter and reset the queue pointers for the Ethernet and serial interfaces.
STEP 19: After the TSYSCLK and RSYSCLK inputs to the T1/E1/J1 transceiver are stable, the receive and
transmit elastic stores should be reset (this step can be skipped if the elastic stores are disabled).
STEP 20: Enable Interrupts as needed.
STEP 21: Begin handling interrupts and latched status events.
9.4 Global Resources
In order to maintain software compatibility with the multiport devices in the product family, a set of global registers
are located at 0F0h-0FFh. The global registers include Global resets, global interrupt status, interrupt masking,
clock configuration, and the Device ID registers. See the Global Register Definitions in
Table 11-2.
9.5 Per-Port Resources
Multiport devices in this product family share a common set of global registers, BERT, and arbiter. All other
resources are per-port.