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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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Register Name:
TR.LIC1
Register Description:
Line Interface Control 1
Register Address:
78h
Bit # 7 6 5 4 3 2 1 0
Name L2 L1 L0 EGL JAS JABDS DJA TPD
Default 0 0 0 0 0 0 0 0
Bits 5 – 7: Line Build-Out Select (L0 to L2). When using the internal termination, the user needs only to select
000 for 75Ω operation or 001 for 120Ω operation below. This selects the proper voltage levels for 75Ω or 120Ω
operation. Using TT0 and TT1 of the TR.LICR4 register, the user can then select the proper internal source
termination. Line build-outs 100 and 101 are for backwards compatibility with older products only.
E1 Mode
L2 L1 L0 Application N (1) Return Loss Rt (1) (Ω)
0 0 0
75Ω normal
1:2 NM 0
0 0 1
120Ω normal
1:2 NM 0
1 0 0
75Ω with high return loss
*
1:2 21dB 6.2
1 0 1
120Ω with high return loss
*
1:2 21dB 11.6
*TT0 and TT1 of LIC4 register must be set to 0 in this configuration.
T1 Mode
L2 L1 L0 Application N (1) Return Loss Rt (1) (Ω)
0 0 0
DSX-1 (0ft to 133ft) / 0dB CSU
1:2 NM
0
0 0 1 DSX-1 (133ft to 266ft) 1:2 NM 0
0 1 0
DSX-1 (266ft to 399ft)
1:2 NM
0
0 1 1 DSX-1 (399ft to 533ft) 1:2 NM 0
1 0 0 DSX-1 (533ft to 655ft) 1:2 NM 0
1 0 1 -7.5dB CSU 1:2 NM 0
1 1 0 -15dB CSU 1:2 NM 0
1 1 1 -22.5dB CSU 1:2 NM 0
Bit 4: Receive Equalizer Gain Limit (EGL). This bit controls the sensitivity of the receive equalizer.
T1 Mode E1 Mode
0 = -36dB (long haul) 0 = -12dB (short haul)
1 = -15dB (limited long haul) 1 = -43dB (long haul)
Bit 3: Jitter Attenuator Select (JAS)
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Bit 2: Jitter Attenuator Buffer Depth Select (JABDS)
0 = 128 bits
1 = 32 bits (use for delay-sensitive applications)
Bit 1: Disable Jitter Attenuator (DJA)
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Bit 0: Transmit Power-Down (TPD)
0 = powers down the transmitter and tri-states the TTIP and TRING pins
1 = normal transmitter operation