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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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5 MAJOR OPERATING MODES
Microprocessor control is possible through the 8-bit parallel control port and provides configuration for all the
features of the device. The Ethernet Link Transport Engine in the device can be configured for HDLC or X.86
encapsulation.
The integrated transceiver can be software configured for T1, E1, or J1 operation. It is composed of a line interface
unit (LIU), framer, two additional HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit
parallel port configured for Intel or Motorola bus operations.
The LIUs are composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is
responsible for generating the necessary waveshapes for driving the network and providing the correct source
impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well
as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for
both 75Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock
and data from the network. The receive sensitivity adjusts automatically to the incoming signal and can be
programmed for 0dB to 43dB or 0dB to 12dB for E1 applications and 0dB to 15dB or 0dB to 36dB for T1
applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter
attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz
MCLK in T1 applications) and can be placed in either transmit or receive data paths.
More information on microprocessor control is available in Section
8.1.