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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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2.14 Test and Diagnostics
• IEEE 1149.1 support
• Programmable on-chip bit error-rate tester (BERT)
• Pseudorandom patterns including QRSS
• User-defined repetitive patterns
• Daly pattern
• Error insertion single and continuous
• Total bit and errored bit counts
• Payload error insertion
• Error insertion in the payload portion of the T1 frame in the transmit path
• Errors can be inserted over the entire frame or selected channels
• Insertion options include continuous and absolute number with selectable insertion rates
• F-bit corruption for line testing
• Loopbacks: remote, local, analog, and per-channel loopback