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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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Register Name:
LI.TQTIE
Register Description:
Serial Interface Transmit Queue Cross Threshold Interrupt Enable
Register Address:
126h
Bit # 7 6 5 4 3 2 1 0
Name - - - - TFOVFIE TQOVFIE TQHTIE TQLTIE
Default 0 0 0 0 0 0 0 0
Bit 3: Transmit FIFO Overflow for Connection Interrupt Enable (TFOVFIE) If this bit is set, the watermark
interrupt is enabled for TFOVFLS.
Bit 2: Transmit Queue Overflow for Connection Interrupt Enable (TQOVFIE) If this bit is set, the watermark
interrupt is enabled for TQOVFLS.
Bit 1: Transmit Queue for Connection High Threshold Interrupt Enable (TQHTIE) If this bit is set, the
watermark interrupt is enabled for TQHTS.
Bit 0: Transmit Queue for Connection Low Threshold Interrupt Enable (TQLTIE) If this bit is set, the
watermark interrupt is enabled for TQLTS.
Register Name:
LI.TQCTLS
Register Description:
Serial Interface Transmit Queue Cross Threshold Latched Status
Register Address:
127h
Bit # 7 6 5 4 3 2 1 0
Name - - - - TFOVFLS TQOVFLS TQHTLS TQLTLS
Default - - - - - - - -
Bit 3: Transmit Queue FIFO Overflowed Latched Status (TFOVFLS) This bit is set if the transmit queue FIFO
has overflowed. This register is cleared after a read. This FIFO is for data to be transmitted from the HDLC to be
sent to the SDRAM.
Bit 2: Transmit Queue Overflow Latched Status (TQOVFLS) This bit is set if the transmit queue has overflowed.
This register is cleared after a read.
Bit 1: Transmit Queue for Connection Exceeded High Threshold Latched Status (TQHTLS) This bit is set if
the transmit queue crosses the High Watermark. This register is cleared after a read.
Bit 0: Transmit Queue for Connection Exceeded Low Threshold Latched Status (TQLTLS) This bit is set if
the transmit queue crosses the Low Watermark. This register is cleared after a read.