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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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14.5 JTAG Functional Timing
This functional timing for the JTAG circuits shows:
• The JTAG controller starting from reset state.
• Shifting out the first 4 LSB bits of the IDCODE.
• Shifting in the BYPASS instruction (111) while shifting out the mandatory X01 pattern.
• Shifting the TDI pin to the TDO pin through the bypass shift register.
• An asynchronous reset occurs while shifting.
Figure 14-3. JTAG Functional Timing
JTCLK
JTRST
JTMS
JTDI
JTDO
(STATE)
Reset
X
Run Test
Idle
Select DR
Scan
Capture
DR
Shift
DR
Exit1
DR
Update
DR
Select DR
Scan
Select IR
Scan
Capture
IR
Shift IR
Exit1
IR
Update
IR
Select DR
Scan
Capture
DR
Shift
DR
Test
Logic Idle
(INST) IDCODE BYPASS
IDCODE
X
X X X
X
Output
Pin
Output pin level change if in "EXTEST" instruction mode