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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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10.11 Channel Blocking Registers
The receive channel blocking registers (TR.RCBR1/TR.RCBR2/TR.RCBR3/TR.RCBR4) and the transmit channel
blocking registers (TR.TCBR1/TR.TCBR2/TR.TCBR3/TR.TCBR4) control RCHBLK and TCHBLK pins,
respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low
during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI
applications. When the appropriate bits are set to a 1, the RCHBLK and TCHBLK pins are held high during the
entire corresponding channel time. Channels 25 through 32 are ignored when the device is operated in the T1
mode.
10.12 Elastic Stores Operation
The device contains dual two-frame elastic stores, one for the receive direction and one for the transmit direction.
Both elastic stores are fully independent. The transmit and receive-side elastic stores can be enabled/disabled
independently of each other. Also, each elastic store can interface to either a 1.544MHz or 2.048MHz/4.096MHz/
8.192MHz/16.384MHz backplane without regard to the backplane rate the other elastic store is interfacing to.
The elastic stores have two main purposes. Firstly, they can be used for rate conversion. When the device is in the
T1 mode, the elastic stores can rate-convert the T1 data stream to a 2.048MHz backplane. In E1 mode, the elastic
store can rate-convert the E1 data stream to a 1.544MHz backplane. Secondly, they can be used to absorb the
differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not locked)
backplane clock, which can be 1.544MHz or 2.048MHz. In this mode, the elastic stores manage the rate difference
and perform controlled slips, deleting or repeating frames of data in order to manage the difference between the
network and the backplane. The elastic stores can also be used to multiplex T1 or E1 data streams into higher
backplane rates.
10.12.1 Receive Elastic Store
See the TR.IOCR1 and TR.IOCR2 registers for information about clock and I/O configurations. If the receive-side
elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin.
The user has the option of either providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin
provide a pulse on frame/multiframe boundaries. If signaling reinsertion is enabled, signaling data in TS16 is
realigned to the multiframe sync input on RSYNC. Otherwise, a multiframe sync input on RSYNC is treated as a
simple frame boundary by the elastic store. The framer always indicates frame boundaries on the network side of
the elastic store by the RFSYNC output, whether the elastic store is enabled or not. Multiframe boundaries are
always indicated by the RMSYNC output. If the elastic store is enabled, then RMSYNC outputs the multiframe
boundary on the backplane side of the elastic store.
10.12.1.1 T1 Mode
If the user selects to apply a 2.048MHz clock to the RSYSCLK pin, then the data output at RSERO is forced to all
1s every fourth channel and the F-bit is passed into the MSB of TS0. Hence, channels 1 (bits 1–7), 5, 9, 13, 17, 21,
25, and 29 [time slots 0 (bits 1–7), 4, 8, 12, 16, 20, 24, and 28] are forced to a 1. Also, in 2.048MHz applications,
the RCHBLK output is forced high during the same channels as the RSERO pin. This is useful in T1-to-E1
conversion applications. If the two-frame elastic buffer either fills or empties, a controlled slip occurs. If the buffer
empties, then a full frame of data is repeated at RSERO, and the TR.SR5.0 and TR.SR5.1 bits are set to a 1. If the
buffer fills, then a full frame of data is deleted, and the TR.SR5.0 and TR.SR5.2 bits are set to a 1.
10.12.1.2 E1 Mode
If the elastic store is enabled, then either CAS or CRC4 multiframe boundaries are indicated through the RMSYNC
output. If the user selects to apply a 1.544MHz clock to the RSYSCLK pin, then every fourth channel of the
received E1 data is deleted and an F-bit position, which is forced to 1, is inserted. Hence, channels 1, 5, 9, 13, 17,
21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) are deleted from the received E1 data stream. Also, in
1.544MHz applications, the RCHBLK output is not active in channels 25 through 32 (i.e., RCBR4 is not active). If
the two-frame elastic buffer either fills or empties, a controlled slip occurs. If the buffer empties, then a full frame of
data is repeated at RSERO, and the TR.SR5.0 and TR.SR5.1 bits are set to a 1. If the buffer fills, then a full frame
of data is deleted, and the TR.SR5.0 and TR.SR5.2 bits are set to a 1.